The present disclosure relates to a driver amplifier circuit which is applied to an interface through which a large-capacity video signal for a television or the like is transmitted, and a communication system using the same.
At the present time, a Low Voltage Differential Signaling (LVDS) interface is generally used in transmission of a large-capacity video signal, for example, in the inside of a television (TV).
In general, a driver amplifier circuit of the LVDS interface is composed of a current source transistor and a current switching transistor for sorting a current generated from the current source transistor into portions.
FIG. 1 is a circuit diagram showing an example of a configuration of a general driver amplifier circuit.
The driver amplifier circuit 1 shown in FIG. 1 includes current switching transistors M1 to M4, current source transistors M5 and M6, inverters INV1 and INV2, input terminals TIN1 and TINB1, output terminals TOUT1 and TOUTB1, and output nodes ND1 and ND2.
Each of the switching transistors M1 and M2, and the current source transistor M5 is composed of a p-channel MOS (PMOS) transistor.
Also, each of the switching transistors M3 and M4, and the current source transistor M6 is composed of an n-channel (NMOS) transistor.
A source terminal of the current source transistor M5 is connected to a power source electric potential VDD, and a source terminal of the current source transistor M5 is connected to a reference electric potential VSS, for example, the grounding electric potential GND.
A gate terminal of the current source transistor M5 is connected to a supply line for a bias voltage Vbp, and a gate terminal of the current source transistor M6 is connected to a supply line for a bias voltage Vpn.
Each of source terminals of the switching transistors M1 and M2 is connected to a drain terminal of the current source transistor M5, and each of source terminals of the switching transistors M3 and M4 is connected to a drain terminal of the current source transistor M6.
A drain terminal of the switching transistor M1, and a drain terminal of the switching transistor M3 are connected to each other, and the output node ND1 is composed of a connection point between both of the drain terminals of the switching transistor M1 and the switching transistor M3. Also, the output node ND1 is connected to the output terminal TOUT1.
A drain terminal of the switching transistor M2, and a drain terminal of the switching transistor M4 are connected to each other, and the output node ND2 is composed of a connection point between both of the drain terminals. Also, the output node ND2 is connected to the output terminal TOUTB1.
A signal IN is supplied to the input terminal TIN1, the input terminal TIN1 is connected to an input terminal of the inverter INV1, and an output terminal of the inverter INV1 is connected to each of gate terminals of the switching transistors M1 and M3.
An inverted signal INB1 of the signal IN is supplied to the input terminal TINB1, the input terminal TINB1 is connected to an input terminal of the inverter INV2, and an output terminal of the inverter INV2 is connected to each of gate terminals of the switching transistors M2 and M4.
In the driver amplifier circuit 1, the signal supplied to the input terminal TIN1 is inverted in level thereof in the inverter INV1, and the resulting inverted signal is supplied as a gate voltage signal PD to each of the gate terminals of the switching transistors M1 and M3.
The inverted signal INB1 of the signal INB supplied to the input terminal TINB1 is inverted in level thereof in the inverter INV2, and the resulting inverted signal is supplied as a gate voltage signal PDB to each of the gate terminals of the switching transistors M2 and M4.
As a result, each of the switching transistors M1 to M4 is turned ON or OFF, currents generated from the current source transistors M5 and M6 are sorted into portions, and signals OUT and OUTB having desired amplitudes are outputted through the output terminals TOUT1 and TOUTB1, respectively.
In the driver amplifier circuit 1 shown in FIG. 1, output voltages of the output signals OUT and OUTB are determined depending on an impedance as will be described below. That is to say, the output voltages of the output signals OUT and OUTB are determined depending on an output current as a current source, and an impedance of a load circuit when the current source transistors M5 and M6 are set at biases at which the current source transistors M5 and M6 enter saturated regions, respectively. Also, the output voltages of the output signals OUT and OUTB are determined depending on ON resistances of the transistors M1 to M6, and the impedance of the load circuit when the current source transistors M5 and M6 are set at biases at which the current source transistors M5 and M6 enter linear regions, respectively.